--VC--	--CR--		--VC--	--CR--		--VC--	--CR--		--VC--	--CR--
00 *	CLC0		20	CLC8		40	WR1		60	WR4
01	CLC1		21	CLC9		41	ACC0		61	WR5
02	CLC2		22	CLC10		42	ACC0		62	WR6
03	CLC3		23	CLC11		43	ACC0		63	WR7
04	CLC4		24	CLC12		44	WR2		64	CSR
05	CLC5		25	CLC13		45	ACC1		65
06	CLC6		26	CLC14		46	ACC1		66	EIR
07	CLC7		27	CLC15		47	ACC1		67	AAR'
10	SLC0		30	SLC8		50	WR3		70	BAR
11	SLC1		31	SLC9		51	ACC2		71
12	SLC2		32	SLC10		52	ACC2		72
13	SLC3		33	SLC11		53	ACC2		73
14	SLC4		34	SLC12		54	ATR		74	AAR
15	SLC5		35	SLC13		55	ACC3		75
16	SLC6		36	SLC14		56	ACC3		76	IIR
17	SLC7		37	SLC15		57	ACC3		77	SR

* Must be 10, 40, or 50 when used in PDT or PCB instructions.

• CLC - Current Location Counter (Read-Write Channel)
• SLC - Starting Location Counter (Read-Write Channel)
• ACC - Floating Point Accumulator
• WR - Working Register (actual address unknown)
• AAR' - Temporary AAR during LCR/SCR/RVI instructions

This implementation provides register memory for all 64 control memory locations. Work registers are not used by this implementation and so may be used for any purpose.

ACC registers are actually shadows of the real data. The simulation formats real data into these registers when they are accessed, and endeavors to update real data when changed. Since three CRs represent a single floating point value, it is possible to get nonsense floating point values if the three CRs are updated inconsistently.