Series 2000 Read/Write Channels

Default non-standard RWC assigment

By default, this implementation does not follow the various Honeywell documentation for specific Read/Write Channels and combinations. Instead, there are 16 fully independent RWCs, with the SLCs (C1 character) numbered 10-17 and 30-37 (CLCs numbered 00-07 and 20-27, respectively). Buffered mode is ignored (bit 40), as is bit 10, so if PDT/PCB instructions expect to use different RWCs then the bits 27 must be unique. PCB instructions may select "no RWC" by using the value 00 or 77. This requires that the value 10 (or 40 or 50) be used to select CLC/SLC 00. Use of 00 or 77 on a PDT instruction will not work.

Standard Honeywell RWC assigment

As an option, the traditional Honeywell mapping of RWC variant character to CLC/SLC registers may be selected. Passing "rwc=map" on the commandline when invoking the simulator will switch to Honeywell mapping. This may be required when running legacy code that makes assumptions about the relationship between the variant character and CLC/SLC registers. Note that "interlock" is still ignored, in the sense that multiple channels are not actually consumed. The primary CLC/SLC is used to perform the I/O. It is not clear if CLC/SLC(s) for the secondary interlocked channel(s) were affected in these cases. A table showing the mapping of variant character to CLC register is found at the end of this page.

General RWC behavior

Simultaneity will exceed that of the original hardware, but should be compatible with any existing software. Also, the degree of simultaneity of specific peripherals is not clear from the documentation available, so best-guesses are made. For example, the magnetic tape drives seem to be completely independent of the control, and so full simultaneity is achieved by using a separate RWC for each drive. However, the disk drives seem to be dependent on resources in the control (unit selection, address register) and thus only one PDT may be active on that control at a time, providing no drive simultaneity. The original hardware may have provided simultaneity for head movement operations (e.g. seek cylinder), but those operations are instantaneous in this implementation.

RWCs are implemented as independent threads. This means a PDT instruction will actually complete before the I/O operation completes, just like original hardware. In addition, the I/O operation, running in the "background" thread, no longer has a guaranteed program context (address mode, relocation, etc). This is why the CLC and SLC registers contain physical addresses. In nearly all cases it is required the issue a PCB instruction to wait for completion, although it is up to the programmer whether that wait is done immediately after the PDT or before the next PDT on the same channel (or in some polling fashion).

The association between channel and perihperal is established when the PDT instruction is executed, and dissolved once the peripheral operation completes (RWC thread terminates). It is not known how a programmer, in a multiprogramming environment, ensures that a RWC does not get re-used between the time an operation completes and the program queries the status with PCB.

For many peripherals, it is possible to return less input data than requested. A program can query the CLC register to determine this, however since these registers contain physical addresses it will normally be necessary to subtract SLC from CLC to yield the length of transfer for comparison.

In the case that a request buffer (RM in memory) was not large enough to contain the peripheral record (typically for Console, Mag Tape, and Disk), the CLC will be pointing to one character past the RM character. To summarize:

When buffer and peripheral record lengths match, CLC will point to the RM character (CLC == RM).
When the buffer is too small, CLC will point to character RM + 1 (CLC > RM). A character would have typically been transferred to the RM location.
When less data was transferred, CLC will point to the character after the last valid character (i.e. CLC will point to some location before the RM character) (CLC < RM).

None of these conditions are considered errors, from the peripheral's perspective. Also, a condition where 0 characters are transferred (CLC == SLC) may exist. If no error was reported by the perihperal, this condition usually means "end of file" (or some other controlled end-of-data condition). Typically, this is for Magnetic Tape and Disk Drives. A 0-length transfer for Console input, for example, would mean the operator simply pressed Carriage Return (entered an empty line).

Standard Honeywell RWC Mapping

C1	MNEMONIC	CLC	C1	MNEMONIC	CLC	C1	MNEMONIC	CLC	C1	MNEMONIC	CLC
00	none	--	20		20*	40	RWC 2'	06	60	RWC 8	00
01	RWC 4'	25	21		21*	41	RWC 1'	05	61	RWC 9'	24
02	RWC 5'+	26	22	RWC 8+	00	42	RWC 2'	06	62	RWC 8+	00
03	RWC 6'+	27	23	RWC 9+	20	43	RWC 3'	07	63	RWC 9+	20
04	RWC 6'	27	24		24*	44	RWC 3'	07	64	RWC 9	20
05	RWC 6'	27	25		25*	45	RWC 3'	07	65	RWC 9	20
06	RWC 6'	27	26	RWC 8'	04	46	RWC 3'	07	66	RWC 9	20
07	RWC 5'	26	27	RWC 9'	24	47		07*	67		27*
10		00*	30		20*	50	RWC 2	02	70	RWC 5	22
11^	RWC 1	01	31^	RWC 4	21	51^	RWC 1+	01	71^	RWC 4+	21
12^	RWC 2	02	32^	RWC 5	22	52^	RWC 2+	02	72^	RWC 5+	22
13^	RWC 3	03	33^	RWC 6	23	53^	RWC 3+	03	73^	RWC 6+	23
14		04*	34		24*	54	RWC 3+	03	74	RWC 6+	23
15^	RWC 1'	05	35^	RWC 4'	25	55	RWC 3+	03	75	RWC 6+	23
16^	RWC 2'	06	36^	RWC 5'	26	56	RWC 3+	03	76	RWC 6+	23
17^	RWC 3'	07	37^	RWC 6'	27	57		07*	77	none	--

+ RWC interlock (not used in simulation)

* For compatability with direct assignment (not a valid Honeywell variant)

^ variant uses same CLC/SLC for both mapped and direct schemes

+	RWC interlock (not used in simulation)
*	For compatability with direct assignment (not a valid Honeywell variant)
^	variant uses same CLC/SLC for both mapped and direct schemes